1. Field of the Invention
The present invention relates to an image signal processing apparatus and method that are favorably used when displaying on a display apparatus image signals obtained by performing A/D conversion processing on analog image signals.
2. Description of the Related Art
Conventionally, when analog image signals are displayed on digital display element such as a liquid crystal display (LCD) panel, it is necessary for the analog image signals to be converted into digital image data by an A/D converter. In this case, the sampling clocks supplied to the A/D converter may be generated by a PLL circuit that is synchronized with a horizontal synchronization signal of the original image signal, however, if there is variation in the sampling clocks because of jitter in the PLL circuit, or jitter in the horizontal synchronization signal or the image signal, then noise appears on the screen.
In order to solve this problem, conventionally, a method is used in which adjustment is performed such that phases of the sampling clocks are shifted and the phase with the least noise is used.
FIG. 5 is a block diagram showing the structure of a conventional image signal processing apparatus that employs the above method.
In FIG. 5, analog image signals (video signals) are input into an A/D converter 1. These image signals may have, for example, a resolution of 1280×1024, a horizontal frequency of 80 KHz, a vertical frequency of 75 Hz, and a sampling rate of 135 MHz. 135 MHz sampling clocks SCK are supplied from a PLL circuit 2 to the A/D converter 1. Digital image data converted by the A/D converter 1 is processed by a signal processing section 8, and then supplied to an LCD panel 9 where it is displayed.
The PLL circuit 2 is formed by a voltage controlled oscillator (VCO) 3 that outputs sampling clocks SCK, a frequency divider 4 that divides the sampling clocks SCK into 1/1688, a delay circuit group 5 that delays the phases of the divided outputs into 32 stages, a switch 6 that selects one of the 32 delayed outputs using the control of the CPU 10, and a phase comparator 7 that performs a phase comparison of the selected divided outputs and a horizontal synchronization signal, and controls the oscillation frequency of the VCO 3 in accordance with the phase difference.
According to the PLL circuit 2 having the above described structure, as a result of the CPU 10 selecting one of the 32 delayed outputs from the delay circuit group 5, it is possible to use the delayed output with the least noise as the sampling clock SCK.
However, even when the above method of adjusting the phases of the sampling clocks is used, if there is a large distortion in the original image waveform, the problem arises that it is not possible to remove the noise sufficiently. In particular, high frequency components may be deleted in image signals output from a PC, and the waveform of one dot (i.e., the waveform of one pixel) may not be a rectangular wave and in some cases may be a triangular wave. If this type of triangular wave is sampled by a sampling clock having a jitter component, a large luminance difference is generated in the sampling data, and the problem arises that noise can be easily generated on the screen.